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NCP1910
V PREF
V PREF
Figure 43. PFC Duty Modulation and Timing Diagram
V ramp + V M ) + V PREF
Z in +
I ch +
V M + V PREF * + V PREF
T (eq. 6)
The PFC modulation and timing diagram is shown in
Figure 43. The MOSFET on time t 1 is generated by the
intersection of reference voltage V PREF and ramp voltage
V ramp . A relationship in Equation 4 is obtained.
I ch t 1
(eq. 4)
C ramp
Where:
? V ramp is the internal ramp voltage, the positive input
of the PFC modulation comparator,
? V M is the multiplier voltage appearing on V M pin,
? I ch is the internal charging current,
? C ramp is the internal ramp capacitor, and
? V PREF is the internal reference voltage, the negative
input of the PFC modulation comparator.
I ch , C ramp , and V PREF also act as the ramp signal of
switching frequency. Hence the charging current I ch is
specially designed as in Equation 5. The multiplier voltage
V M is therefore expressed in terms of t 1 in Equation 6.
C ramp V PREF
(eq. 5)
T
t 1 C ramp V PREF T * t 1
C ramp T
From Equation 3 and Equation 6, the input impedance Z in
is re ? formulated in Equation 7.
V M V bulk
(eq. 7)
V PREF I L ? 50
Because V PREF and V bulk are roughly constant versus
time, the multiplier voltage V M is designed to be
proportional to the I L ? 50 in order to have a constant Z in for
PFC purpose. It is illustrated in Figure 44.
Figure 44. Multiplier Voltage Timing Diagram
It can be seen in the timing diagram in Figure 43 that V M
originally consists of a switching frequency ripple coming
from the inductor current I L . The duty ratio can be
inaccurately generated due to this ripple. This modulation is
the so ? called “peak current mode”. Hence, an external
capacitor C M connected to the multiplier voltage V M pin is
essential to bypass the high ? frequency component of V M .
The modulation becomes the so ? called “average current
mode” with a better accuracy for PFC.
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